Balance testing and balance-testable design of logic circuits

Balance testing and balance-testable design of logic circuits

We propose a low-cost method for testing logic circuits, termed balance testing, which is particularly suited to built-in self testing. Conceptually related to ones counting and syndrome testing, it detects faults by checking the difference between the number of ones and the number of zeros in the test response sequence. A key advantage of balance testing is that the testability of various faul...

Cumulative balance testing of logic circuits

We present a new test response compression method called cumulative balance testing (CBT) that extends both balance testing and accumulator compression testing. CBT uses an accumulated balance signature, and it guarantees very high error coverage (over 99%) for various error models. We demonstrate that the single stuck-line (SSL) fault coverage of CBT for many of the ISCAS 85 combinational benc...

Fault Behaviour and Testable Design of Logic Circuits

Design of Parity Testable Combinational Circuits

The design of random-testable sequential circuits

In general, sequential circuits are considered not to be random-testable. since a required lest sequence may grow exponentially with the number of f1ipflops. and it is very unlikely that a certain sequence occurs at random. This problem can be solved by combining tWO tasks: I) A small pan of the f1ipflops are made directly accessible, for instance by a partial scan path or by a built-in self-te...